1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method of detecting a bit line bridge by selectively floating even- or odd-numbered bit lines.
2. Description of the Related Art
As the integration density of DRAMs is improved, the probability of defects, such as a bit line bridge between memory cells (for example, C1 and C2 illustrated in FIG. 1) increases. The bit line bridge is a phenomenon where a low resistance occurs between adjacent bit lines due to particles or other defects. The low resistance of the bit line bridge occurs when a leakage current flows between adjacent bit lines causing a margin deficiency during a charge-sharing operation of the bit lines and resulting in a device defect.
Conventionally, a bit line bridge is detected by forcing an increase in the current leakage time and increasing the bit line leakage current. However, with this conventional method, when the resistance of the bit line bridge is great, it is difficult to increase the voltage difference between the bit lines since increasing the current leakage time cannot significantly increase the bit line leakage current. Further, although a large voltage difference between bit lines aids the detection of bit line bridges, the high voltage between bit lines can cause unwanted voltage stress.